Single-Input Quadruple-Boosting Switched-Capacitor Nine-Level Inverter with Self-Balanced Capacitors

 Abstract

This paper suggests a single-input switched-capacitor Nine-level inverter configuration advantaging from quadruple voltage-boosting ability, natural voltage balancing of capacitors, and reduced components per level. Also, the single-source character of the proposed topology makes it cheaper and more compact. The cascaded version of the suggested topology has also been introduced, by which high boosting factors, as well as large number of steps, can be obtained. The proposed topology can effectively supply the resistive-inductive or pure inductive load types. The capacitors' impulsive-charging-current issue has been solved by simple small-inductance-based inductor-diode (L-D) networks. The comparative analysis affirms the fewer device-usage in suggested configuration per equal gain or level count than existed structures, resulting in less size and cost. The usage of Nearest-Level modulation guarantees the low- frequency operation of semiconductors and reduces the switching losses. The comparative analysis and experimental outcomes affirm the competitiveness and accurate functionality of suggested configuration.

Index Terms

Multilevel inverter, number of levels, self-balanced capacitors, switched-capacitor, voltage gain.

Proposed Diagram:

Figure 1. Proposed 9-Level Inverter.

Conclusion

This paper has proposed a basic switched-capacitor 9-level inverter that is extendable to higher levels. The single-source nature, quadruple voltage-boosting ability, capacitors' natural charge-balancing, increased levels per device, and capability of feeding low power factor (resistive-inductive or inductive) load types are the main advantages of the suggested topology. The H-bridge switches tolerate Vo;max, but due to their fundamental-frequency operation, their switching- loss is suppressed. The capacitors' impulse-charging current has been reduced by a small-inductance-based L-D net- work. The output voltage THD of the suggested topology is about 8.5%. The comparative analysis confirms that the suggested topology has higher ratios of a number of levels and gain to devices, which is an important advantage. The efficiency of an implemented laboratory-scale prototype of the suggested topology for Vdc D 30 [V] is about 90.9%, which is acceptable. Two extended versions of the suggested basic topology have been introduced to achieve more levels and voltage-gains. The experimental outcomes validate the proper performance of the suggested switched-capacitor 9-level inverter topology.

References

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