A 15 Level Multilevel Inverter with Reduced Number of Switches

Abstract - A new multilevel inverter with reduced number of power switches is proposed. This new multilevel inverter based on cascaded H-bridge topology. This paper reduces total harmonic distortion (THD). This paper proposes a new concept of switching with reduced number of batteries. This concept helps to reduce the complexity of switching compared to other multilevel inverters. Proposed multilevel inverter having fifteen level output is validated with a simple resistive load. The proposed idea has been validated through simulation.

Index Terms

1.      Cascaded H-bridge

2.      15 level inverter

3.      reduced  Switches

Block Diagram:

Fig1.Block diagram of proposed inverter

Expected simulation results:

 

Fig 2: Firing Pulses to Switches S1, S2, S3

Fig.3. Firing Pulses to Switches S4, S5, S6 and S7

 

Fig.4.Simulation output with R load of 15 level

Fig.5.Simulation output with RL load of 15 level

Conclusion

A single phase 15 level reduced switch MLI topology is introduced by various types of operation are studied. A novel SPWM modulation approach is proposed and utilized an proposed topology, the simulation results are verified with a FPGA IP Core Processor based Hardware prototype. The results for the proposed system are explained in the below:

1. The proposed MLI uses only 7switches to give 15 level Output

2. It shown the simulation results that the THD for the Output voltages and current of the proposed system is low and compared to the existing.

3. The proposed system may be used to convert 3-phase 3- line system.

4. For low and medium power applications typical MLI cannot compete with standard UPS at lower level configurations and to the circuit complexity.

The inverter expands by increases the level with minimum number of switches, the overall price is reduced and inverter generates high output voltage. In this paper, fifteen level asymmetric cascaded multilevel inverter is proposed. It generates sinusoidal waveform and generates high voltage .It improves the performance of cascaded multilevel inverter .in this type switching losses are reduced and the total harmonic distortion also reduced.

References

[1] Nabae; I. Takahashi; H. Akagi. ―A new neutralpoint-clamped PWM inverter‖, IEEE Trans. onIndustry Applications, vol. 17, no. 5,pp. 518- 523, 1981.

[2] C.Bharatiraja, R.Latha, Dr.S.Jeevananthan,S.Raghu and Dr.S.S.Dash,”Design And Validation Of Simple Space Vector PWM Scheme For Three-Level NPC - MLI With Investigation Of Dc Link ImbalanceUsing FPGA IP Core‖, Journal of ElectricalEngineering, vol. 13, edition 1, pp 54-63, 2013.

[3] Rodriguez, J.; Jih-Sheng Lai ; Fang ZhengPeng.”Multilevel inverters: a survey of topologies, controls,and applications‖, IEEE Transactions on IndustrialElectronics, vol. 49, no. 4, pp 724-738

[4] P.Jamuna; Dr.C.ChristoberAsirRajan “NewAsymmetrical Multilevel Inverter Based Dynamic Voltage Restorer‖ Journal of Electrical Engineering,vol. 13, edition 1, pp 244-252, 2013.

[5] Nikhil; V.K.; Joseph, K.D. "A Reduced SwitchMultilevel Inverter for Harmonic Reduction", Powerand Energy Engineering Conference (APPEEC), Asia-Pacific, pp 1-4, 2012.